In the display device, a technique for determining a selection order (scan order) of gate lines based on an input image is conventionally proposed in order to achieve low power consumption and downsizing of a power supply circuit. For example, in a technique disclosed in a prior art (for example, see Japanese Patent No. 5,378,613), the scan order of gate lines is determined based on an input image such that a plurality of source lines are driven by drive power smaller than drive power of a plurality of source lines required when a plurality of gate lines are selected in arrangement order.
However, a problem of so-called DC burning arises in the conventional technique. FIGS. 18A-18H are schematic diagrams illustrating a generation principle of the DC burning. FIGS. 18A-18D illustrate pieces of input image data of first to fourth frames, and FIGS. 18E to 18H illustrate the scan order of each of the first to fourth frames. At this point, it is assumed that a display panel is constructed with eight lines. It is also assumed that each frame image is constructed with a white image (255 gradations), a gray image (128 gradations), and a black image (0 gradation). FIG. 19 is a timing chart illustrating gate signal G1 supplied to first gate line GL1 and a source voltage supplied to a pixel of a first line (Line 1). When the first to eighth lines are selected in the scan order as illustrated in FIGS. 18E to 1811, as illustrated in the timing chart of FIG. 19, an average value of source voltages is shifted from a common voltage, and a DC component remains. Consequently, the burning occurs on a display screen.